Sharad Chole, Andrew Fingerhut, Sha Ma, Anirudh Sivaraman, Shay Vargaftik, Alon Berger, Gal Mendelson, Mohammad Alizadeh,
Shang-Tse Chuang, Isaac Keslassy, Ariel Orda and Tom Edsall,
"dRMT: Disaggregated Programmable Switching,"
ACM SIGCOMM, Los Angeles, CA, August 2017.
[slides]
[extended version]
[Also presented at P4 workshop 2017: slides.]
We present dRMT (disaggregated Reconfigurable Match-Action
Table), a new architecture for programmable switches. dRMT overcomes
two important restrictions of RMT, the predominant pipelinebased
architecture for programmable switches: (1) table memory
is local to an RMT pipeline stage, implying that memory not used
by one stage cannot be reclaimed by another, and (2) RMT is hardwired
to always sequentially execute matches followed by actions
as packets traverse pipeline stages. We show that these restrictions
make it difficult to execute programs efficiently on RMT.
dRMT resolves both issues by disaggregating the memory and
compute resources of a programmable switch. Specifically, dRMT
moves table memories out of pipeline stages and into a centralized
pool that is accessible through a crossbar. In addition, dRMT replaces
RMT's pipeline stages with a cluster of processors that can execute
match and action operations in any order.
We show how to schedule a P4 program on dRMT at compile
time to guarantee deterministic throughput and latency. We also
present a hardware design for dRMT and analyze its feasibility and
chip area. Our results show that dRMT can run programs at line rate
with fewer processors compared to RMT, and avoids performance
cliffs when there are not enough processors to run a program at line
rate. dRMT's hardware design incurs a modest increase in chip area
relative to RMT, mainly due to the crossbar.
The GitHub repository of the dRMT project contains all the paper-related scripts.
Extended version of the paper with:.